1. Field of the Invention
The present invention relates to a semiconductor memory device and more specifically to a configuration of a semiconductor memory device including replaceable redundant cells.
2. Description of the Background Art
An example of a conventional semiconductor memory device including redundant cells will be described briefly with reference to FIG. 5.
The conventional semiconductor memory device 9000 shown in FIG. 5 includes a register 901, a row address buffer 902, a redundancy determining circuit 511, a row predecoder 512, a memory cell array 510, a column decoder 903, and a data input/output buffer 904.
Register 901 receives external signals (such as an external row address strobe signal /RAS, an external column address strobe signal /CAS, an external chip select signal /CS, an external write enable signal /WE, an external clock signal CLK, and an external clock enable signal CKE) and outputs corresponding control signals.
In response to an act signal ACT received from register 901, row address buffer 902 outputs a row address signal in accordance with external address signals A0 to Ai.
Memory cell array 510 includes a plurality of memory sub arrays A(0), A(1), . . . , A(n). The memory sub arrays include corresponding normal blocks (NBL(0), NBL(1), . . . , NBL(n)) each formed of normal memory cells and corresponding redundant blocks (RBL(0), RBL(1), . . . , RBL(n)) each formed of redundant cells. Each memory cell in the normal block is connected to a corresponding word line WL. Each redundant cell in the redundant block is connected to a corresponding spare word line SWL.
For a normal block in one memory sub array, replacement using a redundant cell in another memory sub array is allowed.
Redundancy determining circuit 511 determines use/non-use of a redundant cell, and outputs a spare word line enable signal RWLE for selecting spare word line SWL in the redundant block and a word line enable signal NWLE for selecting word line WL in the normal block.
When a redundant cell is to be used, corresponding spare word line enable signal RWLE is activated and corresponding word line enable signal NWLE is inactivated. When a redundant cell is not to be used, spare word line enable signal RWLE is inactivated and corresponding word line enable signal NWLE is activated.
In response to word line enable signal NWLE, row predecoder 512 outputs a decode signal for designating a corresponding word line in accordance with the output of row address buffer 902. Row predecoder 512 also outputs a block select signal for designating a corresponding sense amplifier block and a corresponding normal block in accordance with the output of row address buffer 902.
The conventional semiconductor memory device 9000 shown in FIG. 5 includes the configuration of a shared sense amplifier type. A sense amplifier block 2 is placed between adjacent memory sub arrays. The adjacent memory sub arrays share sense amplifier block 2.
An SA driver 924 and a word line driver 925 are placed for memory cell array 510. Word line driver 925 selects word line WL or spare word line SWL in accordance with the outputs of redundancy determining circuit 511 and row predecoder 512. SA driver 924 outputs a control signal SACnt for controlling activation/inactivation of each sense amplifier block 2.
In accordance with the control of column decoder 903, data input/output buffer 904 transmits and receives signals between data-on input/output pins DQ0 to DQn and memory cell array 510.
Thus, in the conventional semiconductor memory device 9000 shown in FIG. 5, the repair efficiency is enhanced and the occurrence of a defective product is prevented by adopting a configuration allowing replacement with a redundant cell in the same or different memory sub array.
There is the disturb refresh test as a test for semiconductor memory devices. The disturb refresh test repeats reading operation of a word line of interest (repeatedly turns on/off the word line) for a predetermined period to create a situation where leakage is easily caused in a memory cell in the vicinity of the word line of interest. In this manner, the storage state of the memory cell is tested.
Besides the disturb refresh test, there is the disturb refresh acceleration mode test that accelerates the disturb refresh test.
The disturb refresh acceleration mode test carries out a test in a shorter period by simultaneously activating a plurality of word lines.
When the disturb refresh acceleration mode test is performed in conventional semiconductor memory device 9000 above, however, a following problem occurs.
The problem with the disturb refresh acceleration mode test in conventional semiconductor memory device 9000 shown in FIG. 5 will be described with reference to FIG. 6.
Memory cell array 510 includes a plurality of memory sub arrays A(0), . . . , A(n-2-1), A(n/2), . . . , A(n-1), and A(n).
The memory sub arrays include corresponding normal memory blocks (NBL(0), . . . , NBL(/2-1), NBL (n/2), . . . , NBL(n-1), and NBL(n)) and corresponding redundant blocks (RBL(0), . . . , RBL(n/2-1), RBL(n/2), . . . , RBL(n)). Adjacent memory sub arrays share sense amplifier block 2.
It is assumed that a defect in normal block NBL(0) is repaired by spare word line SWL in the redundancy region of memory sub array A(n/2) as shown in FIG. 6.
When word line WL of memory sub array A(0) and word line WL of memory sub array A(n/2) are to be simultaneously activated by the disturb refresh acceleration mode test in this situation, word line WL and spare word line SWL that is for redundancy are simultaneously selected and a defect is caused in memory sub array A(n/2).